Embodiments of the present invention relate to a semiconductor memory device and a method for testing the same.
Generally, a semiconductor memory device stores data in a unit memory cell. The unit memory cell includes a memory element for storing the data therein, and the data is input or output through a bit line to or from the memory element.
Since the semiconductor memory device includes a plurality of unit memory cells, a cell array is comprised of a plurality of unit memory cells, such that data is input and output through bit lines from respective unit memory cells.
In recent times, as the semiconductor memory device becomes highly integrated, one cell array includes an increasing number of unit memory cells, and thus the number of bit lines coupled to the cell array is also increasing.
Since the semiconductor memory device should be designed to include a large number of unit memory cells and a large number of bit lines in a small area, neighboring bit lines may be unavoidably coupled to each other, or parasitic capacitance may occur. As a result, a current may flow in undesired bit lines, such that data is read or written from or in an unexpected or wrong unit memory cell.